History
Itanium Server Sales forecast history.
Development: 1989–2001
In 1989, HP determined that reduced instruction set computer (RISC) architectures were approaching a processing limit at one instruction per cycle. HP researchers investigated a new architecture, later named explicitly parallel instruction computing (EPIC), that allows the processor to execute multiple instructions in each clock cycle. EPIC implements a form of very long instruction word (VLIW) architecture, in which a single instruction word contains multiple instructions. With EPIC, the compiler determines in advance which instructions can be executed at the same time, so the microprocessor simply executes the instructions and does not need elaborate mechanisms to determine which instructions to execute in parallel The goal of this approach is two-fold: first, to enable deeper inspection of the code to identify additional opportunities for parallel execution; and, second, to simplify processor design and reduce energy consumption by eliminating the need for runtime scheduling circuitry.
HP determined that it was no longer cost-effective for individual enterprise systems companies such as itself to develop proprietary microprocessors, so HP partnered with Intel in 1994 to develop the IA-64 architecture, which derived from EPIC. Intel was willing to undertake a very large development effort on IA-64 in the expectation that the resulting microprocessor would be used by the majority of enterprise systems manufacturers. HP and Intel initiated a large joint development effort with a goal of delivering the first product, Merced, in 1998.
During development, Intel, HP, and industry analysts predicted that IA-64 would dominate in servers, workstations, and high-end desktops, and eventually supplant RISC and complex instruction set computer (CISC) architectures for all general-purpose applications. Compaq and Silicon Graphics decided to abandon further development of the Alpha and MIPS architectures respectively in favor of migrating to IA-64.
Several groups developed operating systems for the architecture, including Microsoft Windows, Linux, and UNIX variants such as HP-UX, Solaris, Tru64 UNIX, and Monterey/64 (the latter three were canceled before reaching the market). By 1997, it was apparent that the IA-64 architecture and the compiler were much more difficult to implement than originally thought, and the delivery of Merced began slipping. Technical difficulties included the very high transistor counts needed to support the wide instruction words and the large caches. There were also structural problems within the project, as the two parts of the joint team used different methodologies and had slightly different priorities. Since Merced was the first EPIC processor, the development effort encountered more unanticipated problems than the team was accustomed to. In addition, the EPIC concept depends on compiler capabilities that had never been implemented before, so more research was needed.
Intel announced the official name of the processor, Itanium, on October 4, 1999. Within hours the name Itanic had been coined in an online chat room, a reference to Titanic, the "unsinkable" ocean liner which sank in 1912. Itanic has since often been used by The Register, Scott McNealy and others,implying that the multibillion dollar investment in Itanium—and the tremendous early hype—would be followed by its relatively quick demise.
Original Itanium processor: 2001–02
Original Itanium
Central processing unit
Itanium processor
Produced From June 2001 to June 2002
Common manufacturer(s) Intel
Max CPU clock 733 MHz to 800 MHz
FSB speeds 266 MT/s
Instruction set Itanium
Socket(s) PAC418
Core name(s) Merced
By the time Itanium was released in June, 2001, it was no longer superior to contemporaneous RISC and CISC processors. Itanium competed at the low-end (primarily 4-CPU and smaller systems) with servers based on x86 processors, and at the high end with IBM's POWER architecture and Sun Microsystems' SPARC architecture. Intel repositioned Itanium to focus on high-end business and HPC computing, attempting to duplicate x86's successful "horizontal" market (i.e., single architecture, multiple systems vendors). The success of this initial processor version was limited to replacing PA-RISC and Alpha in HP systems and MIPS in SGI's HPC systems, though IBM also delivered a supercomputer based on this processor. POWER and SPARC remained strong, while the 32-bit x86 architecture continued to grow into the enterprise space. With economies of scale fueled by its enormous installed base, x86 has remained the preeminent "horizontal" architecture in enterprise computing.
Only a few thousand systems using the original Itanium processor were sold, due to relatively poor performance, high cost and limited software availability. Recognizing that the lack of software could be a serious issue moving forward, Intel made thousands of these early systems available to independent software vendors (ISVs) to stimulate development. HP and Intel brought the next-generation Itanium 2 processor to market a year later.
Itanium processor family
Original Itanium logo Original Itanium 2 logo 2006 Itanium 2 logo 2008 Itanium logo
Original logo Version 2 logo 2006 logo 2008 new logo
Itanium 2 processors: 2002–present
The Itanium 2 processor was released in 2002, and was marketed for enterprise servers rather than for the whole gamut of high-end computing. The initial Itanium 2 was codenamed McKinley. McKinley was manufactured using a 180 nm process technology, and relieved many of the performance problems of the original Itanium processor.
In 2003, AMD released the Opteron, which implemented its 64-bit architecture (x86-64). Opteron gained rapid acceptance in the enterprise server space because it provided an easy upgrade from x86. Intel responded by implementing x86-64 in its Xeon microprocessors in 2004. Intel released a new Itanium 2 family member, codenamed Madison, in 2003. Madison used a 130 nm process and was the basis of all new Itanium processors until Montecito was released in June 2006.
In March, 2005, Intel announced that it was working on a new Itanium processor, codenamed Tukwila, to be released in 2007. Tukwila would have four processor cores and would replace the Itanium bus with a new Common System Interface, which would also be used by a new Xeon processor. Intel later said that Tukwila would be delivered in late 2008.
In November 2005, the major Itanium server manufacturers joined with Intel and a number of software vendors to form the Itanium Solutions Alliance to promote the architecture and accelerate software porting.The Alliance announced that its members would invest $10 Billion in Itanium solutions by the end of the decade.
In 2006, Intel delivered Montecito, a dual-core processor that roughly doubled performance and decreased energy consumption by about 20 percent. Quad-core Tukwila processors are still expected to be available to OEMs in late 2008, with systems reaching the marketplace in early 2009.
In comparison with its Xeon family of server processors, Itanium is not a high-volume product for Intel. Intel does not release production numbers, but one industry analyst estimated that the production rate was 200,000 processors per year in 2007.According to Gartner Inc., the total number of Itanium servers sold by all vendors in 2007 was about 55,000. This compares with 417,000 RISC servers (spread across all RISC vendors) and 8.4 million x86 servers. From 2001 through 2007, IDC reports that a total of 184,000 Itanium-based systems have been sold. For the combined POWER/SPARC/Itanium systems market, IDC reports that POWER captured 42% and SPARC captured 32%, while Itanium-based system revenue reached 26% in the second quarter of 2008. According to an IDC analyst, HP currently accounts for perhaps 80% of Itanium systems revenue.
Itanium
Itanium is the brand name for 64-bit Intel microprocessors that implement the Intel Itanium architecture (formerly called IA-64). Intel has released two processor families using the brand: the original Itanium and the Itanium 2. Starting November 1, 2007, new members of the second family are again called Itanium. The processors are marketed for use in enterprise servers and high-performance computing systems. The architecture originated at Hewlett-Packard (HP) and was later developed by HP and Intel together.
Itanium's architecture differs dramatically from the x86 architectures (and the x86-64 extensions) used in other Intel processors. The architecture is based on explicit instruction-level parallelism, in which the compiler makes the decisions about which instructions to execute in parallel. By contrast, other superscalar architectures depend on elaborate processor circuitry to keep track of instruction dependencies during runtime. This alternative approach helps current Itanium processors execute up to six instructions per clock cycle.
After a protracted development process, the first Itanium processor, codenamed Merced, was released in 2001, and more powerful Itanium processors have been released periodically. HP produces most Itanium-based systems, but several other manufacturers have also developed systems based on Itanium. As of 2007, Itanium is the fourth-most deployed microprocessor architecture for enterprise-class systems, behind x86-64, IBM POWER, and SPARC. Intel released its newest Itanium, codenamed Montvale, in November 2007, and has announced plans to release a quad-core Itanium processor (code-named Tukwila) to server OEMs in late 2008. Systems based on the new processor are expected to be available in early 2009, more than a year later than Intel's initial projection
Itanium's architecture differs dramatically from the x86 architectures (and the x86-64 extensions) used in other Intel processors. The architecture is based on explicit instruction-level parallelism, in which the compiler makes the decisions about which instructions to execute in parallel. By contrast, other superscalar architectures depend on elaborate processor circuitry to keep track of instruction dependencies during runtime. This alternative approach helps current Itanium processors execute up to six instructions per clock cycle.
After a protracted development process, the first Itanium processor, codenamed Merced, was released in 2001, and more powerful Itanium processors have been released periodically. HP produces most Itanium-based systems, but several other manufacturers have also developed systems based on Itanium. As of 2007, Itanium is the fourth-most deployed microprocessor architecture for enterprise-class systems, behind x86-64, IBM POWER, and SPARC. Intel released its newest Itanium, codenamed Montvale, in November 2007, and has announced plans to release a quad-core Itanium processor (code-named Tukwila) to server OEMs in late 2008. Systems based on the new processor are expected to be available in early 2009, more than a year later than Intel's initial projection
Processors
Processors
Released processors
The Itanium processors show a steady progression in capability. Merced was a proof of concept. McKinley dramatically improved the memory hierarchy and allowed Itanium to become reasonably competitive. Madison, with the shift to a 130 nm process, allowed for enough cache space to overcome the major performance bottlenecks. Montecito, with a 90 nm process, allowed for a dual-core implementation and a major improvement in performance per watt. Montvale added three new features: core-level lockstep, demand-based switching and front-side bus frequency of up to 667 MHz.
Codename
process released Clock L2 Cache/
core L3 Cache/
core Bus dies/
device cores/
die watts/
device comments
Itanium
Merced
180 nm 2001-06 733 MHz 96 KB none 266 MHz 1 1 116 2MB off-die L3 cache
800 MHz none 130 4MB off-die L3 cache
Itanium 2
McKinley
180 nm 2002-07-08 900 MHz 256 KB 1.5 MB 400 MHz 1 1 130 HW branchlong
1 GHz 3 MB 130
Madison
130 nm 2003-06-30 1.3 GHz 3 MB 130
1.4 GHz 4 MB 130
1.5 GHz 6 MB 130
2003-09-08 1.4 GHz 1.5 MB 130
2004-04 1.4 GHz 3 MB 130
1.6 GHz 3 MB 130
Deerfield
130 nm 2003-09-08 1.0 GHz 1.5 MB 62 Low voltage
Hondo
130 nm 2004-Q1 1.1 GHz 4 MB 400 MHz 2 1 260 32 MB L4
Fanwood
130 nm 2004-11-08 1.6 GHz 3 MB 533 MHz 1 1 130
1.3 GHz 3 MB 400 MHz 62? Low voltage
Madison 9M
130 nm 2004-11-08 1.6 GHz 9 MB 400 MHz 130
2005-07-05 1.67 GHz 6 MB 667 MHz 130
2005-07-18 1.67 GHz 9 MB 667 MHz 130
Montecito
90 nm 2006-07-18 1.4 GHz 256 KB+
1 MB 12 MB 400 MHz 1 2 104 Virtualization,
Multithread,
no HW IA-32
1.6 GHz 12 MB 533 MHz 1 2 104
Montvale
90 nm 2007-10-31 1.66 GHz 4-18 MB 400-667 MHz 1 1-2 75-104 Core-level lockstep,
demand-based switching
Future processors
This section contains information about scheduled or expected future computer chips.
It may contain preliminary or speculative information, and may not reflect the final specification of the product.
According to Gartner, "...the future roadmap for Itanium looks as strong as that of any RISC peer like Power or SPARC." Based on available information, the future of the Itanium processor family apparently lies in multi-core chips. As of May 2008, some information is known for the following:
* Tukwila will be released in late 2008. One report indicates that the device will use a 65 nm process, include four cores, 30 MB on-die caches, Hyper-Threading technology and dual integrated memory controllers, and will implement double-device data correction, which helps to fix memory errors. Tukwila will also implement Intel QuickPath Interconnect, a new memory interface that replaces the Itanium bus. It will have a peak interprocessor bandwidth of 96 GB/s and a peak memory bandwidth of 34 GB/s. QuickPath is used on Intel processors using the Nehalem architecture starting with the Core i7 in November 2008, so Tukwila will probably be able to use the Intel X58 and other chipsets used by Nehalem.
* Poulson will be the follow-on processor to Tukwila. It will use a 32 nm silicon process technology and will feature four or more cores, multithreading enhancements, and new instructions to take advantage of parallelism, especially in virtualization. It is due around 2010.
* Kittson will follow Poulson. Few details are known other than the existence of the codename.
Released processors
The Itanium processors show a steady progression in capability. Merced was a proof of concept. McKinley dramatically improved the memory hierarchy and allowed Itanium to become reasonably competitive. Madison, with the shift to a 130 nm process, allowed for enough cache space to overcome the major performance bottlenecks. Montecito, with a 90 nm process, allowed for a dual-core implementation and a major improvement in performance per watt. Montvale added three new features: core-level lockstep, demand-based switching and front-side bus frequency of up to 667 MHz.
Codename
process released Clock L2 Cache/
core L3 Cache/
core Bus dies/
device cores/
die watts/
device comments
Itanium
Merced
180 nm 2001-06 733 MHz 96 KB none 266 MHz 1 1 116 2MB off-die L3 cache
800 MHz none 130 4MB off-die L3 cache
Itanium 2
McKinley
180 nm 2002-07-08 900 MHz 256 KB 1.5 MB 400 MHz 1 1 130 HW branchlong
1 GHz 3 MB 130
Madison
130 nm 2003-06-30 1.3 GHz 3 MB 130
1.4 GHz 4 MB 130
1.5 GHz 6 MB 130
2003-09-08 1.4 GHz 1.5 MB 130
2004-04 1.4 GHz 3 MB 130
1.6 GHz 3 MB 130
Deerfield
130 nm 2003-09-08 1.0 GHz 1.5 MB 62 Low voltage
Hondo
130 nm 2004-Q1 1.1 GHz 4 MB 400 MHz 2 1 260 32 MB L4
Fanwood
130 nm 2004-11-08 1.6 GHz 3 MB 533 MHz 1 1 130
1.3 GHz 3 MB 400 MHz 62? Low voltage
Madison 9M
130 nm 2004-11-08 1.6 GHz 9 MB 400 MHz 130
2005-07-05 1.67 GHz 6 MB 667 MHz 130
2005-07-18 1.67 GHz 9 MB 667 MHz 130
Montecito
90 nm 2006-07-18 1.4 GHz 256 KB+
1 MB 12 MB 400 MHz 1 2 104 Virtualization,
Multithread,
no HW IA-32
1.6 GHz 12 MB 533 MHz 1 2 104
Montvale
90 nm 2007-10-31 1.66 GHz 4-18 MB 400-667 MHz 1 1-2 75-104 Core-level lockstep,
demand-based switching
Future processors
This section contains information about scheduled or expected future computer chips.
It may contain preliminary or speculative information, and may not reflect the final specification of the product.
According to Gartner, "...the future roadmap for Itanium looks as strong as that of any RISC peer like Power or SPARC." Based on available information, the future of the Itanium processor family apparently lies in multi-core chips. As of May 2008, some information is known for the following:
* Tukwila will be released in late 2008. One report indicates that the device will use a 65 nm process, include four cores, 30 MB on-die caches, Hyper-Threading technology and dual integrated memory controllers, and will implement double-device data correction, which helps to fix memory errors. Tukwila will also implement Intel QuickPath Interconnect, a new memory interface that replaces the Itanium bus. It will have a peak interprocessor bandwidth of 96 GB/s and a peak memory bandwidth of 34 GB/s. QuickPath is used on Intel processors using the Nehalem architecture starting with the Core i7 in November 2008, so Tukwila will probably be able to use the Intel X58 and other chipsets used by Nehalem.
* Poulson will be the follow-on processor to Tukwila. It will use a 32 nm silicon process technology and will feature four or more cores, multithreading enhancements, and new instructions to take advantage of parallelism, especially in virtualization. It is due around 2010.
* Kittson will follow Poulson. Few details are known other than the existence of the codename.
Successor
Successor
Intel Core 2
The Pentium D brand was succeeded on July 27, 2006 by the Core 2 branded line of microprocessors with the Core microarchitecture released as dual- and quad-core CPUs branded Duo, Quad, and Extreme.
Implementation
In a single-processor scenario, the CPU-to-northbridge link is point-to-point and the only real requirement is that it is fast enough to keep the CPU fed with data from memory.
When assessing the Pentium D, it is important to note that it is essentially two CPUs in the same package and that it will face the same bus contention issues as a pair of Xeons prior to the Dual Independent Bus architecture introduced with the Dual-Core Dempsey Xeons. To use a crude analogy one could say that instead of using a single cable between CPU and north bridge, one must use a Y-splitter. Leaving aside advanced issues such as cache coherency, each core can only use half of the 800 MT/s FSB bandwidth when under heavy load.
Comparison to Pentium Dual-Core
Intel subsequently released a new line of processors based on the Core architecture under the name Pentium Dual Core. While the new Pentium Dual-Core processors boast considerably less wattage consumption opposed to the Pentium D (Using only 65W with Pentium D using 95W or 130W), it only has 1MiB L2 Cache memory while Pentium D boasts up to a 2x2 MiB L2 Cache memory. It should be noted that despite these differences, the Pentium dual-core still outperforms the Pentium D with most applications.
Intel Core 2
The Pentium D brand was succeeded on July 27, 2006 by the Core 2 branded line of microprocessors with the Core microarchitecture released as dual- and quad-core CPUs branded Duo, Quad, and Extreme.
Implementation
In a single-processor scenario, the CPU-to-northbridge link is point-to-point and the only real requirement is that it is fast enough to keep the CPU fed with data from memory.
When assessing the Pentium D, it is important to note that it is essentially two CPUs in the same package and that it will face the same bus contention issues as a pair of Xeons prior to the Dual Independent Bus architecture introduced with the Dual-Core Dempsey Xeons. To use a crude analogy one could say that instead of using a single cable between CPU and north bridge, one must use a Y-splitter. Leaving aside advanced issues such as cache coherency, each core can only use half of the 800 MT/s FSB bandwidth when under heavy load.
Comparison to Pentium Dual-Core
Intel subsequently released a new line of processors based on the Core architecture under the name Pentium Dual Core. While the new Pentium Dual-Core processors boast considerably less wattage consumption opposed to the Pentium D (Using only 65W with Pentium D using 95W or 130W), it only has 1MiB L2 Cache memory while Pentium D boasts up to a 2x2 MiB L2 Cache memory. It should be noted that despite these differences, the Pentium dual-core still outperforms the Pentium D with most applications.
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