Processors

Processors

Released processors

The Itanium processors show a steady progression in capability. Merced was a proof of concept. McKinley dramatically improved the memory hierarchy and allowed Itanium to become reasonably competitive. Madison, with the shift to a 130 nm process, allowed for enough cache space to overcome the major performance bottlenecks. Montecito, with a 90 nm process, allowed for a dual-core implementation and a major improvement in performance per watt. Montvale added three new features: core-level lockstep, demand-based switching and front-side bus frequency of up to 667 MHz.
Codename
process released Clock L2 Cache/
core L3 Cache/
core Bus dies/
device cores/
die watts/
device comments
Itanium
Merced
180 nm 2001-06 733 MHz 96 KB none 266 MHz 1 1 116 2MB off-die L3 cache
800 MHz none 130 4MB off-die L3 cache
Itanium 2
McKinley
180 nm 2002-07-08 900 MHz 256 KB 1.5 MB 400 MHz 1 1 130 HW branchlong
1 GHz 3 MB 130
Madison
130 nm 2003-06-30 1.3 GHz 3 MB 130
1.4 GHz 4 MB 130
1.5 GHz 6 MB 130
2003-09-08 1.4 GHz 1.5 MB 130
2004-04 1.4 GHz 3 MB 130
1.6 GHz 3 MB 130
Deerfield
130 nm 2003-09-08 1.0 GHz 1.5 MB 62 Low voltage
Hondo
130 nm 2004-Q1 1.1 GHz 4 MB 400 MHz 2 1 260 32 MB L4
Fanwood
130 nm 2004-11-08 1.6 GHz 3 MB 533 MHz 1 1 130
1.3 GHz 3 MB 400 MHz 62? Low voltage
Madison 9M
130 nm 2004-11-08 1.6 GHz 9 MB 400 MHz 130
2005-07-05 1.67 GHz 6 MB 667 MHz 130
2005-07-18 1.67 GHz 9 MB 667 MHz 130
Montecito
90 nm 2006-07-18 1.4 GHz 256 KB+
1 MB 12 MB 400 MHz 1 2 104 Virtualization,
Multithread,
no HW IA-32
1.6 GHz 12 MB 533 MHz 1 2 104
Montvale
90 nm 2007-10-31 1.66 GHz 4-18 MB 400-667 MHz 1 1-2 75-104 Core-level lockstep,
demand-based switching

Future processors
This section contains information about scheduled or expected future computer chips.
It may contain preliminary or speculative information, and may not reflect the final specification of the product.

According to Gartner, "...the future roadmap for Itanium looks as strong as that of any RISC peer like Power or SPARC." Based on available information, the future of the Itanium processor family apparently lies in multi-core chips. As of May 2008, some information is known for the following:

* Tukwila will be released in late 2008. One report indicates that the device will use a 65 nm process, include four cores, 30 MB on-die caches, Hyper-Threading technology and dual integrated memory controllers, and will implement double-device data correction, which helps to fix memory errors. Tukwila will also implement Intel QuickPath Interconnect, a new memory interface that replaces the Itanium bus. It will have a peak interprocessor bandwidth of 96 GB/s and a peak memory bandwidth of 34 GB/s. QuickPath is used on Intel processors using the Nehalem architecture starting with the Core i7 in November 2008, so Tukwila will probably be able to use the Intel X58 and other chipsets used by Nehalem.
* Poulson will be the follow-on processor to Tukwila. It will use a 32 nm silicon process technology and will feature four or more cores, multithreading enhancements, and new instructions to take advantage of parallelism, especially in virtualization. It is due around 2010.

* Kittson will follow Poulson. Few details are known other than the existence of the codename.