Background

Background

As a product concept, the Celeron was introduced in response to Intel's loss of the low-end market, in particular to Cyrix's 6x86, AMD's K6, and IDT Winchip. Intel's existing low-end product, the Pentium MMX, was no longer performance competitive at 233 MHz. Although a faster Pentium MMX would have been a lower-risk strategy, the industry standard Socket 7 platform hosted a market of competitor CPUs which could be drop-in replacements for the Pentium MMX. Instead, Intel pursued a budget part that was pin-compatible with their high-end Pentium II product, using the Pentium II's (Slot 1) interface. The Celeron was used in many low end machines and, in some ways, became the standard for non gaming computers.
Intel Celeron processor family
Original Logo New Logo Desktop Laptop
Code-named Core Date released Code-named Core Date released
Original Celeron brand logo New logo as of 2006 Covington
Mendocino
Coppermine
Tualatin
Willamette
Northwood
Conroe-L (250nm)
(250nm)
(180nm)
(130nm)
(180nm)
(130nm)
(65nm) Apr 1998
Aug 1998
Mar 2000
Oct 2001
May 2002
Sep 2002
Jun 2007 Mendocino
Coppermine
Tualatin
Northwood
Yonah-512
Merom (250nm)
(180nm)
(130nm)
(130nm)
(65nm)
(65nm) Jan 1999
Feb 2000
Apr 2002
Jun 2002
Apr 2006
Jan 2007
Original Celeron M logo New logo as of 2006 Banias
Dothan
Yonah
Merom (130nm)
(90nm)
(65nm)
(65nm) Jan 2004
Aug 2004
Apr 2006
Jan 2007
Original Celeron D logo New logo as of 2006 Prescott
Cedar Mill (90nm)
(65nm) Jun 2004
May 2006
New logo as 2008 Allendale dual (65nm) Jan 2008 Merom dual (65nm) Jul 2008
List of Intel Celeron microprocessors

Celeron (P6)

Covington

The first Covington Celeron was essentially a 266 MHz Deschutes Pentium II manufactured without any secondary cache at all. Covington also shared the 80523 product code of Deschutes. Although clocked at 266 or 300 MHz (frequencies 33 or 66 MHz higher than the desktop version of the Pentium w/MMX), the cacheless Celerons were a good deal slower than the parts they were designed to replace. Substantial numbers were sold on first release, largely on the strength of the Intel name, but the Celeron quickly achieved a poor reputation both in the trade press and among computer professionals. The initial market interest faded rapidly in the face of its poor performance and with sales at a very low level, Intel felt obliged to develop a substantially faster replacement as soon as possible. Nevertheless the first Celerons were quite popular among some overclockers, for their flexible overclockability and reasonable price. Covington was only manufactured in slot 1 SEPP format.

Mendocino
Celeron 300A (SEPP package)
Top of a Mendocino-core Socket 370 Celeron (PPGA package)
Underside of a Mendocino-core Socket 370 Celeron.

The Mendocino Celeron, launched 24 August 1998, was the first mass-market CPU to use on-die L2 cache.Whereas Covington had no secondary cache at all, Mendocino included 128 KiB of L2 cache running at full clock rate. The first Mendocino-core Celeron was clocked at a then-modest 300 MHz but offered almost twice the performance of the old cacheless Covington Celeron at the same clock rate. To distinguish it from the older Covington 300 MHz, Intel called the Mendocino core Celeron 300A. Although the other Mendocino Celerons (the 333 MHz part, for example) did not have an "A" appended, some people call all Mendocino processors "Celeron-A" regardless of clock rate.

The new Mendocino core Celeron was a good performer from the outset. Indeed, most industry analysts regarded the first Mendocino-based Celerons as too successful—performance was sufficiently high to not only compete strongly with rival parts, but also to attract buyers away from Intel's high-profit flagship, the Pentium II. Overclockers soon discovered that, given a high-end motherboard, the Celeron 300A could run reliably at 450 MHz. This was achieved by simply increasing the Front Side Bus (FSB) clock rate from the stock 66 MHz to the 100 MHz clock of the Pentium II. At this frequency, the Mendocino Celeron rivaled the fastest x86 processors available.

At the time on-die cache was difficult to manufacture; especially L2 as more of it is needed to attain an adequate level of performance. A benefit of on-die cache is that it operates at the same clock rate as the CPU. All other Intel CPUs at that time used motherboard mounted or slot mounted secondary L2 cache, which was very easy to manufacture, cheap, and simple to enlarge to any desired size (typical cache sizes were 512 KiB or 1 MiB), but they carried the performance penalty of slower cache performance, typically running the FSB at a frequency of 60 to 100 MHz for motherboard mounted L2 cache. The implementation of the Pentium II's 512 KiB of L2 cache was unique at the time, comprising moderately high-performance L2 cache chips mounted on a special-purpose board alongside the processor itself, running at half the processor's performance and communicating with the CPU through a special backside bus. This method of cache placement was expensive and imposed practical cache-size limits, but allowed the Pentium II to be clocked higher and avoided front side bus RAM/L2 cache contention typical with motherboard-placed L2 cache configurations.

Over time, newer Mendocino processors were released at 333, 366, 400, 433, 466, 500, and 533 MHz. The "Mendocino" Celeron CPU came only designed for a 66 MHz frontside bus, but this would not be a serious performance bottleneck until clock rates reached higher levels.

The Mendocino Celerons also introduced new packaging. When the Mendocinos debuted they came in both a Slot 1 SEPP and Socket 370 PPGA package. The Slot 1 form had been designed to accommodate the off-chip cache of the Pentium II and had mounting problems with motherboards. Because all Celerons are a single-chip design, however, there was no reason to retain the slot packaging for L2 cache storage, and Intel discontinued the Slot 1 variant: beginning with the 466 MHz part, only the PPGA Socket 370 form was offered. (Third-party manufacturers made motherboard slot-to-socket adapters (nicknamed Slotkets) available for a few dollars, which allowed, for example, a Celeron 500 to be fitted to a Slot 1 motherboard.) One interesting note about the PPGA Socket 370 Mendocinos is that SMP (symmetric multiprocessing) mode was available, and there was at least one motherboard released (the ABIT BP6) which took advantage of this fact.

The Mendocino also came in a mobile variant, with clock rates from 266, 300, 333, 366, 400, 433, 466, 500, 533, and 600 MHZ.

In Intel's "Family/Model/Stepping" scheme, Mendocino CPUs are family 6, model 6 and their Intel product code is 80524. These identifiers are shared with the related Dixon Mobile Pentium II variant.

Coppermine-128
Celeron Coppermine 128 with 600 MHz (FC-PGA package)

Underside of a Celeron Coppermine 128, 600 MHz

The next generation Celeron was the Coppermine-128 (sometimes known as the "Celeron II"). These were a derivative of Intel's Coppermine Pentium III and were released on March 29, 2000. Like the Mendocino, the Celeron-128 used 128 KiB of on-chip L2 cache and was (initially) restricted to a 66 MHz Front Side Bus Speed, But the big news was the addition of SSE instructions, due to the new Coppermine core. Other than half the L2 cache (128 KiB instead of 256 KiB) and a lower FSB (66 to 100 MHz instead of 100 to 133 MHz), the Coppermine Celeron was identical to the Coppermine Pentium III.

All Coppermine-128s were produced in the same FCPGA Socket 370 format that most Coppermine Pentium III CPUs used. These Celeron processors began at 533 MHz and continued through 566, 600, 633, 666, 700, 733, and 766 MHz. Because of the limitations of the 66 MHz bus, there were diminishing returns on performance as clock rates increased. On January 3, 2001, Intel switched to a 100 MHz bus with the launch of the 800 MHz Celeron, resulting in a significant performance-per-clock improvement.All Celeron-128 CPUs from 800 MHz and higher use the 100 MHz front side bus. Various models were made at 800, 850, 900, 950, 1000, and 1100 MHz.

In Intel's "Family/Model/Stepping" scheme, Coppermine Celerons and Pentium IIIs are family 6, model 8 and their Intel product code is 80526.

Tualatin-256
A Tualatin core Celeron 1200 MHz (Tualeron) (FC-PGA2 package)

These Celeron processors, released initially at 1200 MHz (1.2 GHz) on October 2, 2001,were based on Pentium III Tualatin core and made with a 0.13 micrometer process for the FCPGA2 socket 370 . They were nicknamed "Tualeron" — a portmanteau of the words Tualatin and Celeron. Some software and users refer to the chips as "Celeron-S", referring to the chip's lineage with the Pentium III-S, but this is not an official designation. Intel later released 1000 MHz and 1100 MHz parts (which were given the extension "A" to their name to differentiate them from the Coppermine-128 of the same clock rate they replaced). A 1,300 MHz chip, launched January 4, 2002, and finally a 1,400 MHz chip, launched May 15, 2002 (the same day as the Netburst Willamette 1.7 GHz Celeron launch), marked the end of the Tualatin-256 line.

With regards to core functionality, Tualatin-256 was again quite similar to its Pentium III sibling. The most significant differences were a lower 100 MHz bus and only 256 KiB of L2 cache (whereas the Pentium III had either 256 KiB or 512 KiB of L2 cache). Furthermore, the Tualeron's L2 cache had a higher latency which boosted manufacturing yields for this budget CPU.

Despite offering much improved performance over the Coppermine Celeron it superseded, the Tualatin Celeron still suffered stiff competition from AMD's Duron budget processor. Intel later responded by releasing the Netburst Willamette Celeron, and for some time Tualatin Celerons were manufactured and sold in parallel with their replacement Pentium 4-based Celerons.

In Intel's "Family/Model/Stepping" scheme, Tualatin Celerons and Pentium IIIs are family 6, model 11 and their Intel product code is 80530.